1. Field of the Invention
The present invention relates to a D/A (digital-to-analog) conversion device and method which are applicable to a charged particle beam scanning deflector of a charged particle beam exposure apparatus and relates to a charged particle beam exposure apparatus and method.
2. Description of the Prior Art
A charged particle beam exposure apparatus requires higher accuracy of exposure position for purposes of finer patterning. The exposure apparatus also has to reduce exposure standby time and thereby improve exposure throughput since it scans a charged particle beam for patterning.
Incidentally, a D/A conversion circuit is interposed between a control circuit and a deflector for controlling the charged particle beam since a digital signal is used to control the scanning of the charged particle beam. However, the D/A conversion circuit is limited in performance. Deterioration in input-output linearity of the D/A conversion circuit often occurs and thus renders high-precision control difficult.
A D/A conversion device improved to overcome this difficulty is disclosed in Japanese Patent Application Laid-Open Publication No. Hei 10-290162.
A D/A conversion device 10A disclosed in FIG. 4 in Japanese Patent Application Laid-Open Publication No. Hei 10-290162 includes a first D/A conversion circuit 11 which receives input of 16-bit digital data and outputs a corresponding electric signal, a memory 13A which stores correction codes for all digital data that can be represented by 16 bits, and a second D/A conversion circuit 12 which receives input of the correction code for the digital data from the memory 13A and outputs a corresponding electric correction signal. Both the first and second D/A conversion circuits 11 and 12 are current output mode circuits. The first D/A conversion circuit 11 is configured of an R-2R ladder resistor network for the low-order 12 bits and a decoder for the high-order 4 bits, as shown in FIG. 14 of Japanese Patent Application Laid-Open Publication No. Hei 10-290162.
The D/A conversion device 10A is configured so that the electric output signal from the first D/A conversion circuit 11 is corrected by the electric correction signal from the second D/A conversion circuit 12.
The D/A conversion device performs operation as disclosed in FIG. 5 of Japanese Patent Application Laid-Open Publication No. Hei 10-290162.
The operation is prepared beforehand by inputting all digital data that can be represented by 16 bits to the first D/A conversion circuit 11, determining measured values corresponding to the digital data, and determining deviations from an ideal curve. The deviations are added, and their sum is stored in the memory 13A as a correction code for the digital data.
Then, digital data is inputted to the first D/A conversion circuit 11, which in turn outputs an electric output signal in analog form.
Also, the digital data is used to address the memory 13A that stores the correction codes, and the correction code corresponding to the digital data is read from the memory 13A.
Then, the read correction code is inputted to the second D/A conversion circuit 12, which in turn outputs an electric correction signal in analog form.
The electric correction signal is added to or subtracted from the electric output signal from the first D/A conversion circuit 11 to thereby correct the electric output signal.
However, the D/A conversion device mentioned above requires much time since time for access to the memory 13A is involved in each and every input of the correction code to the second D/A conversion circuit 12. The D/A conversion device also requires a memory having such a large capacity as can store correction codes for all digital data that can be represented by the configuration bits.